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- Article name
- An interleaving algorithm for a distributed shared cache of a multi-core processor with an arbitrary number of banks
- Authors
- Pikov V. A., , pikov@ya.ru, Moscow Aviation Institute (National Research University), Moscow, Russia
Nedbailo Yu. A., , yuri.nedbailo@mail.ru, Joint Stock Company «MCST», Moscow, Russia
Surchenko A. V., , Alexander.V.Surchenko@mcst.ru, Joint Stock Company «MCST», Moscow, Russia
- Keywords
- microprocessor / chip multiprocessor / cache memory / interleaving
- Year
- 2023 Issue 3 Pages 59 - 67
- Code EDN
- SPLRCO
- Code DOI
- 10.52190/2073-2600_2023_3_59
- Abstract
- A cache interleaving algorithm has been developed that supports an arbitrary number of banks. Experiments on 40-, 48- and 56-core processor models in SPEC CPU2017 tests showed the advantage of the proposed algorithm over the traditional division-based algorithm by an average of about 1 percent of processor performance.
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